The present invention concerns a semiconductor integrated circuit device technique and, more in particular, it relates to a useful technique to be applied to portable equipment, such as portable telephones and handy type personal computers, for which there is a strong trend toward reducing the size, the weight and the thickness of the product.
Recently, a trend toward reducing the size, the weight and the thickness of the product has become vigorous for electronic equipment along with an improved function and performance. This is largely due to a rapid increase in the use of personal equipment, such as personal telephones or handy type personal computers in recent years. Further, man-machine interface functions have been increased in personally manipulated equipment, for which easy handlability and operability have been considered increasingly important. It is considered that the trend will become more and more conspicuous in expected regular multimedia areas.
Under such circumstances, development for increasing the density and the degree of integration of semiconductor chips has progressed continuously, however the size and the number of electrodes of the semiconductor chips have increased, while the size of the packages have also increased rapidly. Accordingly, narrowing of the pitch of terminal leads has been promoted for facilitating the size reduction of the packages, which makes mounting of the package more difficult.
In view of the above, it has been proposed in recent years to provide high density packages with super-multiple pins having the same area as that of the semiconductor chips, and such packaging techniques are mentioned, for example, in various publications, such as xe2x80x9cNikkei Microdevicexe2x80x9d p 98-p 102, issued on May 1, 1994, xe2x80x9cNikkei Microdevicexe2x80x9d p 96-p 97, issued on Feb. 1, 1995 by Nikkei BPCO and xe2x80x9cElectronic Materialxe2x80x9d, p 22-p 28, issued on Apr. 1, 1995 (Heisei 7) by Kogyo Chosakai. One example of the structures produced with such packaging techniques, for example, as described in FIG. 6 of the xe2x80x9cElectronic Materialxe2x80x9d publication, has a package structure in which a flexible wiring substrate is disposed by way of an elastomer (elastic material) on the surface of a semiconductor chip, leads on one end of wirings of the flexible wiring substrate are electrically connected with bonding pads on the surface of the semiconductor chip, and bump lands on the other end of the wirings of the flexible wiring substrate are electrically connected with the solder bumps.
The package structure has an outer size about equal to or greater than that of a semiconductor chip by the size of a protection frame optionally attached to the periphery of the chip, for which a flexible wiring substrate formed with solder bumps is used. The wiring pattern of the wiring substrate is made of a Cu foil having a Au plating on one side, the top ends of which to be connected with the pad of the chip constitute a lead pattern which is only composed of Au as a result of etching the Cu foil. In this structure, the flexible wiring substrate is bonded by an elastomer on the surface of the semiconductor chip and then the Au leads are connected with the bonding pads of the semiconductor chip.
In a study made by the present inventor of the package structure as described above, the following problems were recognized. For example, since the flexible wiring substrate in the package structure described above has a structure typically represented by a TCP (Tape Carrier Package) in which a Cu wiring pattern is formed on the surface of a polyimide tape, and an elastomer is formed to the wiring substrate on the side of the wiring surface, it is difficult to mount the elastomer uniformly and stably because of unevenness of the wiring pattern on the flexible wiring substrate. That is, there exist such problems that voids not filled with the elastomer are formed near both sides of the protrusions of the wiring pattern upon coating or appending the elastomer on the flexible wiring substrate, and the step of bonding the semiconductor chip can not be conducted stably since the size and the shape of the elastomer are not stable.
Further, bump electrodes are formed on the wiring substrate on the side of the tape. That is, a bump electrode is connected with the wirings by way of a through hole formed in the tape. Since the thickness of the tape is relatively large, for example, as much as 50 xcexcm, if the pitch between the bump electrodes is smaller than the thickness of the tape, the aspect ratio of the through hole is increased to bring about a concern that the bump electrode and the wiring will not be connected. Accordingly, there is a concern that an increase in the number of pins of the package may be restricted.
In view of the above, an object of the present invention is to provide a semiconductor integrated circuit device capable of mounting an elastic structural material to a wiring substrate stably with a high accuracy and making the bonding step of a semiconductor chip stable, thereby enabling assembling with a high yield.
Another object of the present invention is to provide a technique for promoting an increase in the number of pins in a package.
An object of the present invention is to provide a semiconductor integrated circuit device capable of obtaining excellent electrical properties in view of noise resistance by the adoption of a multiple wiring layer structure.
An object of the present invention is to prevent wiring from becoming contaminated ingredients of an elastic structural material.
An object of the present invention is to prevent a semiconductor chip from being damaged, improve the reliability of the semiconductor chip, as well as prevent connection failure between an elastic structural material and the semiconductor chip, worsening of the flatness of the wiring substrate and lowering of reliability.
An object of the present invention is to eliminate a requirement for a soft-modified special wire bonder and to effect a shortening of the contact time upon bonding by further simplifying the trace of the bonding tool.
An object of the present invention is to solve a problem concerning disconnection of wirings.
An object of the present invention is to reduce any damage to a passivation layer or a semiconductor chip therebelow and further improve the bondability by preventing contamination of the wirings.
An object of the present invention is to increase the bonding strength between wirings and a substrate material and obtain a stable notch cutting performance.
An object of the present invention is to suppress warp of a wiring substrate and improve bondability with a bonding material, so as to constitute a package of excellent moisture proofness and reliability.
An object of the present invention is to improve the groove-fillage capability of an elastic structural material, capable of increasing the strength of a metal mask, by using a plurality of one side bridging portions, and further improving the groove-fillage capability by the formation of a stopping dam for sealant flow.
An object of the present invention is to improve the bondability and prevent damage to a semiconductor chip in an inner lead bonding technique.
An object of the present invention is to form a suitable S-shaped configuration with no return of a bonding tool but by merely driving the bonding tool vertically using a wiring design which takes into consideration a bending stress ratio.
An object of the present invention is to reduce the occurrence of cracks in wirings per se and moderate bonding damage to a semiconductor chip.
An object of the present invention is to suppress bleeding of low molecular weight ingredients of an elastic structural material and further avoid a disadvantage involving the creation of voids upon forming the elastic structural material by surface flattening.
An object of the present invention is to improve the fabrication accuracy for hole diameter for connection of a bump electrode in a method of manufacturing a semiconductor integrated circuit.
An object of the present invention is to provide a technique for forming a semiconductor package which is capable of bonding bump electrodes more satisfactorily, reducing the pitch of the bump electrodes and which provides output terminals at a higher density in a method of manufacturing a semiconductor integrated circuit device.
These and other objects, as well as novel features of the present invention will become apparent by consideration of the descriptions in the specification with reference to the accompanying drawings.
Among the features disclosed in the present application, a summary of typical examples will be explained simply as follows.
That is, one of the semiconductor integrated circuit devices according to the present invention provides a package structure applied to a semiconductor integrated circuit device in which a wiring substrate is disposed by way of an elastic structural material on a main surface of a semiconductor chip, lead portions on one end of the wirings of the wiring substrate are electrically connected with external terminals on the main surface of the semiconductor chip, and land portions on the other end of the wirings of the wiring substrate are electrically connected with bump electrodes, wherein the wiring substrate has wirings formed on the main surface of a substrate base material (tape), and an elastic structural material is disposed opposite to the main surface of the substrate base material.
Further, the bump electrodes are formed on the side of the wirings.
Further, the bump electrodes are connected with the wirings each by way of a through hole disposed in an insulation film formed on the wirings and having a thickness smaller than that of the wiring base material.
Further, the external terminals of the semiconductor chip are disposed at a central portion or at an outer circumferential portion of the semiconductor chip, and the bump electrodes connected to the external terminals of the semiconductor chip by way of the wirings of the wiring substrate are disposed to the inside, outside or in both regions inside and outside with respect to the outer circumference of the semiconductor chip.
Further, in a semiconductor integrated circuit device of the present invention, the size of the end of the elastic structural member of the semiconductor chip on the side of the externals terminal and the end of the substrate base material of the wiring substrate is determined based on the ingredients of the elastic structural material.
Further, in a semiconductor integrated circuit device of the present invention, a distance M2 between the end of the substrate base material of the wiring substrate and the end of the elastic structural material on the outer circumferential side of the semiconductor integrated circuit device, and a distance M1 between the end of the semiconductor chip and the end of the substrate base material are determined within a range capable of satisfying the relationship:
M1 greater than M2 greater than 0 
Further, in a semiconductor integrated circuit device of the present invention, the wirings of the wiring substrate are formed to such a shape that a portion fixed with the substrate base material of the wiring substrate and a top end portion connected to the external terminals of the semiconductor chip are displaced at least by more than the width of the wirings.
Further, in a semiconductor integrated circuit device of the present invention, the wirings of the wiring substrate are formed as a cantilever structure fixed at one side to the substrate base material of the wiring substrate.
Further, in a semiconductor integrated circuit device of the present invention, the size of the end of an opening in a surface protection film on the semiconductor chip is determined within such a range that the wirings do not interfere with the surface protection film at least on the side thereof on which a bonding tool is driven down.
Further, in a semiconductor integrated circuit device of the present invention, the wirings of the wiring substrate are formed such that an effective area of a wiring portion of the wiring on the side of the notch terminal end is made larger. Particularly, the wiring portion on the side of the notch terminal end is connected with an opposed land portion of the wirings, or is extended longitudinally or laterally in a vacant region of the wirings, or adjacent wirings are connected with each other.
Further, in a semiconductor integrated circuit device of the present invention, the elastic structural material is formed within a range greater over the entire circumference at least by more than the width of a protrusion at the outer circumferential portion formed in the elastic structural material.
Further, in a semiconductor integrated circuit device of the present invention, when the elastic structural material is formed in two parts so as not to be bonded on the external terminals of the semiconductor chip, each of the ends of spaces to which the divided elastic structural materials are opposed is formed in a groove-shape. Particularly, a plurality of grooves are formed at each of the ends of the elastic structural material, or a stepping dam for sealant flow is previously formed during a sealing step.
Further, in a semiconductor integrated circuit device of the present invention, the connection structure between the external terminals of the semiconductor chip and the wirings of the wiring substrate are formed by previously forming stud bumps on the external terminals of the semiconductor chip, and the external terminals of the semiconductor chip and the wirings of the wiring substrate are connected by way of the stud bumps.
Further, in a semiconductor integrated circuit device of the present invention, the connection structure between the external terminals of the semiconductor chip and the wiring substrate is formed by previously supplying solder so as to surround the wirings of the wiring substrate and the external terminals of the semiconductor chip, and the external terminals of the semiconductor chip are connected by way of the solder.
Further, in a semiconductor integrated circuit device of the present invention, the connection structure between the external terminal of the semiconductor chip and the wirings of the semiconductor substrate are formed by connecting the wirings of the wiring substrate and the external terminals of the semiconductor chip by way of stud bumps by using stud bumps of solder or Au ball so as to surround the wirings of the wiring substrate from above.
Further, in a semiconductor integrated circuit device of the present invention, the connection structure between the external terminals of the semiconductor chip and the wirings of the wiring substrate are formed by connecting the wirings of the wiring substrate and the external terminals of the semiconductor chip by using Al, solder or Au wire.
Further, in a semiconductor integrated circuit device of the present invention, the wiring structure of the wiring substrate is formed by narrowing the lateral size of the wirings from the end of the substrate base material of the wiring substrate to the top end of the wirings, such that the bending stress ratio a is represented by:
xcex1="sgr"1/"sgr"0 
where "sgr"0 is bending strength caused at the end of the substrate base material and "sgr"1 is maximum stress caused at an intermediate portion between the end of the substrate base material and the top end of the wirings, and wherein the lateral size is made constant particularly from a predetermined position, and the size and the shape of the wirings are determined such that the bending stress ratio a is from 1.2 to 1.5 in a case where the bending stress ratio xcex1 is represented by the following formula:
xcex1=b1xc3x97(L2xe2x88x92L1)/(b2xc3x97L2) 
in which L1 is a taper length, L2 is a wiring length, b1 is a taper width and b2 is a wiring width.
Further, in a semiconductor integrated circuit device of the present invention, the wiring structure of the wiring substrate is formed by using an electroconductive material as a core material and applying Au plating on the surface.
Further, the wiring structure of the wiring substrate is formed by using Cu as a core material, applying Au plating on the surface and making at least one end connected with the external electrodes of the chip into a S-shaped configuration.
Further, in a semiconductor integrated circuit device of the present invention, a flattening insulation film is formed on the wiring substrate on the side of the wirings and an elastic structural material is disposed on the insulation film.
Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention comprises a step of forming an elastic structural material on the rear face of a wiring substrate (tape side) in which wirings are formed on the substrate base material (tape), a step of bonding a semiconductor chip to the surface of the elastic structural material so as to oppose the wiring substrate, a step of connecting one end of the wirings to the external terminals of the semiconductor chip, a step of forming an insulation film thinner than the substrate base material on a main surface of the wirings, a step of forming openings to the insulation film each at a position corresponding to the other end of the wirings to be joined with the bump electrodes, and a step of forming the bump electrodes being joined to the other end of the wirings by way of the wirings.